Memory cell access devices and methods of making the same

ABSTRACT

Planar access transistor devices and recessed access transistor devices used with semiconductor devices may include gate electrodes having materials with multiple work functions, materials that are electrically isolated from each other and supplied with two or more voltage supplies, or materials that create a diode junction within the gate electrode. Access device drivers are also provided which are capable of driving distinct or identical voltages to the gate electrodes.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to MOSFET devices and, in particular, to planaraccess devices and recessed access devices for semiconductor devices andmethods of making the same.

2. Technical Background

Semiconductor devices employ access devices to store and retrieve datastored in memory circuits. The access devices may include semiconductorstructures such as transistor devices, and can be in the form of planaror recessed access device structures. The gate electrode of an accessdevice is biased, by an access device driver circuit, providing “on” and“off” states for the access device and facilitating the access andstorage of data in the memory circuit utilizing the access devices. Whenthe device is “on,” current is allowed to flow through the accessdevice, and therefore the transistor is in inversion. When the device is“off,” current is supposed to be blocked from flowing through the accessdevice, and therefore the transistor is in accumulation.

FIG. 1 illustrates a conventional planar access device (PAD) ortransistor device, used with semiconductor memory circuits. A gate stack60 is formed over a semiconductor substrate 50. The gate stack 60includes a gate oxide layer 62, a gate electrode 64, an insulator cap66, and sidewall spacers 68. Source and drain regions 54 are located oneither side of the gate stack 60 forming the transistor device.

FIG. 2 illustrates a conventional recessed access device (RAD) used withsemiconductor memory circuits. The RAD structure includes a gate stack70 formed in trenches of a semiconductor substrate 50. The gate stack 70includes a gate oxide layer 72, a gate electrode 74, an insulator cap76, and sidewall spacers 78. Source and drain regions 54 are located oneither side of the gate stack 70 forming the RAD device.

The PAD and RAD structures illustrated in FIGS. 1 and 2 may be used asaccess devices for memory circuits. As the dimensional requirements ofsemiconductor structures continue to diminish in size, fabricationprocesses are developed to accommodate the shrinking dimensions. For amemory circuit, utilizing either a PAD or RAD structure as the accessdevice, there are three major undesirable leakage paths in thetransistor: subthreshold leakage, gate induced drain leakage (GIDL), andjunction leakage. Each leakage type occurs when the access device is inaccumulation, or the “off” state. Subthreshold leakage is the leakage ofcharge between the source and drain of the access device and increaseswith smaller transistor dimensions, specifically the effective length ofthe gate in an access device. One way of reducing the subthresholdleakage is to apply a more negative voltage to the gate electrode of theaccess device in the “off” state. For example, in an “off” state, anegative voltage is applied to the PAD gate electrode 64 or the RAD gateelectrode 74, illustrated in FIGS. 1 and 2 respectively. However, theapplication of a more negative voltage to the gate electrode results inhigher GIDL current in the access device. Another way of reducing thesubthreshold leakage is to apply a more negative voltage to thesubstrate 50. However, the application of a more negative voltage to thesubstrate results in increased junction leakage. Subthreshold leakagemay also be decreased by employing a high work function differencebetween the source and drain regions and a gate electrode, for exampleby employing a P+ gate and an N+ source/drain region. However, GIDLcurrent increases in such cases.

Furthermore, the RAD gate stack 70, and the use of RAD gate stacks 70with semiconductor devices, increases the effective length of a gate inan access device compared to the PAD gate stack 60. The increased lengthof the gate tends to decrease the amount of subthreshold leakage in theaccess device. However, the GIDL current from the RAD gate stack 70 isgreater than the GIDL current of PAD gate stack 60. It is believed thatthe increased amount of GIDL loss in the RAD gate stack 70 is the resultof the increased overlap of the source/drain regions 54 with the gateelectrode 74.

Therefore, it is desirable to develop an access device for use withmemory devices and other semiconductor devices that may be able toreduce subthreshold leakage, junction leakage, and gate induced drainleakage simultaneously. It is also desirable to develop processes forfabricating such devices using conventional semiconductor fabricationprocesses.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

While the specification concludes with claims particularly pointing outand distinctly claiming that which is regarded as the present invention,this invention can be more readily understood and appreciated by one ofordinary skill in the art from the following description of theinvention when read in conjunction with the accompanying drawings inwhich:

FIG. 1 illustrates a cross-sectional view of a conventional planaraccess device such as a memory access device;

FIG. 2 illustrates a cross-sectional view of a conventional recessedaccess device such as a memory access device;

FIG. 3 illustrates a cross-sectional view of a planar access deviceaccording to embodiments of the invention;

FIGS. 4A-4E illustrate cross-sectional views of various process steps inthe fabrication of the planar access device illustrated in FIG. 3according to embodiments of the invention;

FIG. 5 illustrates a cross-sectional view of a recessed access devicestructure according to embodiments of the invention;

FIGS. 6A-6E illustrate cross-sectional views of various process steps inthe fabrication of the recessed access device structure illustrated inFIG. 5 according to embodiments of the invention;

FIG. 7A illustrates a cross-sectional view of a recessed access devicestructure according to embodiments of the invention;

FIGS. 7B-7D illustrate cross-sectional views of various process steps inthe fabrication of the recessed access device structure illustrated inFIG. 7A according to embodiments of the invention;

FIG. 7E illustrates a cross-sectional view of a spherical recessedaccess device structure according to embodiments of the invention;

FIG. 8 illustrates a cross-sectional view of a planar access deviceaccording to embodiments of the invention;

FIGS. 9A-9D illustrate cross-sectional views of various process steps inthe fabrication of the planar access device illustrated in FIG. 8according to embodiments of the invention;

FIG. 10 illustrates a cross-sectional view of a recessed access devicestructure according to embodiments of the invention;

FIGS. 11A-11D illustrate cross-sectional views of various process stepsin the fabrication of the recessed access device illustrated in FIG. 10according to embodiments of the invention;

FIG. 12 illustrates an access device driver according to embodiments ofthe invention which may be used to supply voltages to a planar orrecessed access device;

FIG. 13 illustrates an access device driver according to embodiments ofthe invention which may be used to supply voltages to a planar orrecessed access device;

FIG. 14 illustrates a cross-sectional view of a planar access deviceaccording to embodiments of the invention;

FIGS. 15A-15D illustrate cross-sectional views of various process stepsin the fabrication of the planar access device illustrated in FIG. 14according to embodiments of the invention;

FIG. 16 illustrates a cross-sectional view of a recessed access deviceaccording to embodiments of the invention; and

FIGS. 17A-17D illustrate cross-sectional views of various process stepsin the fabrication of the recessed access device of FIG. 16 according toembodiments of the invention.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments of the invention relate to planar and recessed accesstransistor devices used in semiconductor devices. More particularly,embodiments of the invention relate to planar and recessed accessdevices that may be used with CMOS semiconductor devices or memorydevices such as DRAM memory devices. However, the embodiments of theinvention are not limited to such devices as the planar and recessedaccess devices of the invention may be used with any semiconductordevice.

According to some embodiments of the invention, a planar or recessedaccess device may include a gate electrode having two or more gatematerials wherein each of the gate materials has a different workfunction than the other gate materials of the gate electrode. Thepresence of the two or more work functions in the gate electrode mayhelp to reduce the amount of gate induced drain leakage that occurs inthe gate stack or recessed access device. Furthermore, the reduction ofthe gate induced drain leakage may be accomplished without sacrificingadditional losses due to subthreshold leakage or junction leakage, whichis controlled by the difference and margin bias provided by thedifferent work function materials in the gate electrode.

According to other embodiments of the invention, a planar or recessedaccess device may include a gate electrode having two or moreelectrically isolated regions. The electrically isolated regions of thegate electrode may be supplied by different voltage supplies such thatdifferent voltages may be supplied to and across the length of a gateelectrode. Further, the same voltage may be supplied to each of theelectrically isolated regions. The planar and recessed access devicesmay be turned into an “on” state or an “off” state depending upon thevoltages supplied by the different voltage supplies.

The electrically isolated regions allow different margin biases to besupplied to different portions of the gate electrode, which in turn maybe used to control gate induced drain leakage in the planar or recessedaccess device. In addition, the voltages supplied to the electricallyisolated regions during the “on” state and “off” state may be altered tocontrol the subthreshold leakage and junction leakage of the planar orrecessed access device. In this manner, the gate induced drain leakagemay be controlled or reduced without sacrificing losses to subthresholdleakage and junction leakage.

According to still other embodiments of the invention, a planar orrecessed access device may include a gate electrode having a cathoderegion and an anode region, wherein the cathode and anode form a diodein the gate electrode. Each of the cathode and anode may be connected toseparate voltage supplies such that different or similar voltages may besupplied to and across the length of the gate electrode. The voltagessupplied to the anode and cathode may be tailored such that when thegate stack or recessed access device is in an “off” state the gateinduced drain leakage is minimized. The margin bias provided across thediode may also be used to minimize the subthreshold leakage and junctionleakage.

In still other embodiments of the invention, an access device driver isprovided, wherein the access device driver may supply two or morevoltages to a planar or recessed access device. Access device driversaccording to embodiments of the invention may be able to providedissimilar or similar voltages to a planar or recessed access devicehaving two or more electrically isolated regions in a gate electrode orto a gate electrode comprising a diode. The control of voltages to theplanar or recessed access device by the access device driver mayfacilitate the control of the gate induced drain leakage, subthresholdleakage, and junction leakage of a planar or recessed access device.

According to embodiments of the invention, an access device of a memorycell includes one or more gates in a memory or semiconductor device thatare capable of reducing an amount of gate induced drain leakage (GIDL)in the access device. An access device may include a gate electrode orgate diode capable of accepting two voltages simultaneously. In otherembodiments, the access device may include gate electrodes comprisingtwo or more materials having different work functions.

According to some embodiments of the invention, gate-induced drainleakage may be reduced by forming an access device or transistor gatestack from materials having differing work functions. For example, anaccess device or gate stack may be formed from two or more materialshaving dissimilar work functions. A material having a higher workfunction may be used to form those portions of the gate stack wheresub-threshold leakage is problematic while a material having a lowerwork function may be used to form those portions of the gate stack wheregate-induced drain leakage is a concern. For example, a gate stackhaving two or more gate materials may be formed such that a gatematerial closest to a storage capacitor has a lower work function thanthe gate material closest to the bitline of a memory device. Thedissimilar work function materials may be separated by a barrier layerand strapped together by a metal or conductive strap. The barrier layermay comprise a conductive material and may serve as a conductive strap.

Unlike conventional planar access devices which employ a material havinga consistent work function to form a gate electrode or gate stack of anaccess device, embodiments of the present invention may employ one ormore materials in the gate stack of an access device to decrease orcontrol GIDL. For example, access devices according to embodiments ofthe invention may be used in semiconductor devices as planar accessdevices or transistors incorporated with memory devices. Embodiments ofthe invention are especially useful in memory devices such as in dynamicrandom access memory (DRAM) devices but are not limited to such use.

An access device 100 according to embodiments of the invention isillustrated in FIG. 3. The access device 100 may include one or moregate stacks 120 formed over a semiconductor substrate 110. Gate stacks120 may include an oxide layer 121 and a gate electrode over the oxidelayer. The gate electrode may include a first gate material 122 having afirst work function associated therewith and a second gate material 124having a second work function associated therewith. As illustrated inFIG. 3, the gate materials may be separated by a barrier layer 123. Oneor more straps 126 may overlie the first gate material 122 and secondgate material 124. The straps 126 may provide an electrical connectionbetween the first and second gate materials. A gate stack 120 may alsoinclude an insulator cap 130 and sidewall spacers 128 as known and usedwith conventional planar access devices. The gate stacks 120 may overliesource and drain regions 112 in the semiconductor substrate 110.

The semiconductor substrate 110 may include semiconductor substratesconventionally used with or for the fabrication of memory devices,access devices, and other semiconductor devices. In many embodiments,the semiconductor substrate 110 may include a silicon-containingstructure such as silicon, silicon-on-insulator structures, andsilicon-on-sapphire structures.

Oxide layer 121 may include any oxide material that may be used to formoxide layers 121 capable of being used with conventional gate stacksdevices and particularly with gate stacks or other transistor devicesintegrated with memory devices or semiconductor devices.

The gate electrodes of embodiments of the invention may include multiplegate materials. As illustrated in FIG. 3, a gate electrode may include afirst gate material 122 and a second gate material 124. Preferably, thefirst gate material 122 and the second gate material 124 have differingwork functions. Use of gate materials having differing work functions toform the gate electrodes may reduce the effects of gate induced drainleakage (GIDL) in the access device 100. For example, the first gatematerial 122 of the gate stack 120 illustrated in FIG. 3 may include anN+ doped polysilicon material and the second gate material 124 mayinclude a P+ doped polysilicon material. The N+ doping of the first gatematerial 122 provides the first gate material 122 with a lower workfunction than the P+ doped material of the second gate material 124. TheP+ second gate material 124 maintains a high threshold voltage V_(t) forthe access device 100, thereby reducing the subthreshold leakage whilethe N+ first gate material 122 decreases the GIDL in the access device100.

Although embodiments of the invention have been described having twogate materials it is understood that the gate electrodes may be formedof two or more gate materials. For example, a gate electrode may includegate materials having differing work functions in a horizontalcross-section of the gate electrode as illustrated in FIG. 3 as well asdiffering work functions in a vertical cross-section of the gateelectrode. The first gate material, for example, may include a varyingwork function across a vertical cross-section from the oxide layer 121to the insulator cap 130. Similarly, the second gate material 124 mayinclude a varying work function across a vertical cross-section from theoxide layer 121 to the insulator cap 130.

A separator 123 may be positioned between the first gate material 122and the second gate material 124 and may include insulating materials,conductive materials, metals, or other materials capable of separatingthe gate materials. For example, separator 123 may be formed of anitride, an oxide, silicide, a conductive metal, or a metallic alloy. Insome embodiments, the separator 123 may prevent cross-diffusion of thefirst gate material 122 with the second gate material 124 or preventcross-diffusion of dopants between the gate materials, especially duringsubsequent heating processes utilized in the fabrication of asemiconductor device.

In some embodiments, the strap 126 may be a conductive strap providingan electrical connection between the first gate material 122 and thesecond gate material 124. Exemplary materials that may be used as aconductive strap 126 include metals, as well as conductive siliconmaterials, doped silicon materials including conductively dopedpolycrystalline silicon, and other conductors. In other embodiments, thestrap 126 need not be conductive. For instance, if the separator 123provides an electrical connection between the first gate material 122and the second gate material 124, the strap 126 may not provide anelectrical connection between the gate materials. In those embodimentswhere such an electrical connection between the first gate material 122and the second gate material 124 exists, a conductive strap 126 is notnecessary but may be used.

The insulator cap 130 of the gate stacks 120 may include any insulatingmaterial that may be used as an insulating layer for conventional planardevices. For instance, the insulator cap 130 may be formed of a nitrideor an oxide, such as silicon dioxide.

Similarly, the sidewall spacers 128 may be formed from materials used toform spacers 128 with conventional gate stack devices and access devices100. For example, the spacers 128 may include materials such as silicondioxide or other oxides, silicon nitride, or other nitrides, or siliconoxynitride.

The gate stacks 120 of embodiments of the invention may be producedusing fabrication processes used to form conventional semiconductordevices and particularly memory devices. For example, the gate stacksillustrated in FIG. 3 may be formed using conventional CMOS or memorydevice fabrication processes as illustrated in FIGS. 4A-4E. Asillustrated in FIG. 4A, a polysilicon layer 122A may be deposited over agate oxide layer 121 overlying a semiconductor substrate 110. Thepolysilicon layer 122A may then be masked and etched according toconventional processes to form the first gate material 122 of the gatestack 120 as illustrated in FIG. 4B. A separator layer 123A may bedeposited over the first gate material 122 and the semiconductorsubstrate 110. Etching of the separator layer 123A leaves the separator123 formed on the sides of the first gate material 122. A secondpolysilicon material 124A may be deposited over the first gate material122, the separator 123, and the semiconductor substrate 110 asillustrated in FIG. 4C. Masking and etching of the second polysiliconmaterial 124A may result in the formation of the second gate material124 of the gate stacks 120 as illustrated in FIG. 4D. A strap material126A deposited over the first gate material 122, separator 123, andsecond gate material 124 as illustrated in FIG. 4D may be masked andetched to form the strap 126 illustrated in FIG. 4E. Conventionalmasking, etching, doping, and deposition processes may be used tocomplete the formation of the gate stacks 120 including the formation ofthe insulator caps 130 and sidewall spacers 128, and the doping of theactive areas 112.

Although methods for forming the gate stacks 120 of particularembodiments of the invention are illustrated in FIGS. 4A-4E, it isunderstood that other methods and processes may also be used tofabricate gate stacks 120 according to embodiments of the invention. Inaddition, it is understood that the order of formation of the first gatematerial 122, separator 123, and second gate material 124 is onlyexemplary. The gate materials 122 and 124, and the separator 123, may beformed in any desired order. Furthermore, the first gate material 122and the second gate material 124 may be formed simultaneously out of thesame polysilicon material. Subsequent doping of the first gate material122 and second gate material 124 may establish a desired difference inwork function of the two materials. In addition, the oxide layer 121overlying the semiconductor substrate 110 may be a continuous oxidelayer (not shown) which may be etched or otherwise removed during thefabrication process.

According to other embodiments of the invention, an access device 150may include one or more recessed access device (RAD) structures 170wherein the RAD structures 170 include two or more materials havingdifferent work functions. For example, exemplary RAD structures 170according to embodiments of the invention are illustrated in FIG. 5.

The RAD structures 170 may be formed in trenches of a semiconductorsubstrate 160 between active areas 162 such as source and drain regionsor bitlines and storage capacitors for memory devices. The trenches inthe semiconductor substrate 160 may be lined with a gate-oxide 171 asused with conventional RAD structures. The RAD structures 170 mayinclude a first gate material 172 overlying a second gate material 174in a trench of the semiconductor substrate 160. The first gate material172 and the second gate material 174 may be separated by a metal barrier173 or other conductive barrier as illustrated in FIG. 5. The RADstructures 170 may also include a strap 176 overlying the first gatematerial 172 and an insulator cap 180 overlying the strap 176. Gateelectrode sidewall spacers 178 may also be formed with the RADstructures 170 to complete the trenched gate stack 170.

According to embodiments of the invention, the second gate material 174of the RAD structures 170 may be formed of a material having a higherwork function than the first gate material 172. For example, the secondgate material 174 used to form the RAD structures 170 illustrated inFIG. 5 may include a P+ doped polysilicon material and the first gatematerial 172 may include an N+ doped polysilicon material. Othermaterials having differing work functions may also be used to form RADstructures 170 according to embodiments of the invention.

The metal barrier 173 between the first gate material 172 and the secondgate material 174 may provide an ohmic contact between the two gatematerials. The metal barrier 173 may include metals such as tungsten,aluminum, copper, or titanium. In some embodiments, the metal barrier173 may be formed from one or more metal layers. The metal layers mayinclude similar or dissimilar metals. In other embodiments, the metalbarrier 173 may be substituted with a barrier material (not shown) thatmay provide an electrical connection or conduction between the firstgate material 172 and the second gate material 174. In addition, thebarrier material may prevent diffusion of dopants between the two gatematerials. The barrier layer may also be an insulator or may includelayers of conductors, conductors and insulators, or insulators.

In some embodiments, the strap 176 may be a conductive material, such asa metal, a conductive silicon material, a doped silicon material, oranother conductor. In other embodiments, the strap 176 need not beconductive.

The insulator cap 180 of the RAD structures 170 may include anyinsulating material that may be used as an insulating layer forconventional planar or recessed access devices. For instance, theinsulator cap 180 may be formed of a nitride or an oxide such as silicondioxide.

Similarly, the sidewall spacers 178 may be formed from materials used toform spacers 178 with conventional planar or recessed access devices.For example, the sidewall spacers 178 may include materials such assilicon dioxide or other oxides, silicon nitride, or other nitrides, orsilicon oxynitride.

The RAD structures 170 of embodiments of the invention may be producedusing fabrication processes used to form conventional semiconductordevices and particularly memory devices. For example, the RAD structures170 illustrated in FIG. 5 may be formed using conventional CMOS ormemory device fabrication processes similar to the steps illustrated inFIGS. 6A-6E. As illustrated in FIG. 6A, a semiconductor substrate 160having trenches formed therein may be provided. Oxide 171 may be grownin the trenches as used with conventional RAD structures. A polysiliconlayer 174A may be deposited over the semiconductor substrate 160 and inthe trenches. Masking and/or etching of the polysilicon layer 174A maybe performed to form the second gate material 174 in the bottoms of thetrenches of the semiconductor substrate 160 as illustrated in FIG. 6B. Abarrier layer 173A may be deposited over the second gate material 174and the semiconductor substrate 160. Masking and/or etching of thebarrier layer 173A may form the metal barrier 173 over the second gatematerial 174 in the bottom of the trenches as illustrated in FIG. 6C. Asecond polysilicon layer 172A may be deposited over the semiconductorsubstrate 160 and in the trenches over the metal barrier 173 asillustrated in FIG. 6C. Masking and/or etching of the second polysiliconlayer 172A may form the first gate material 172 as illustrated in FIG.6D. The masking and/or etching of the second polysilicon layer 172A maybe performed such that a portion of the first gate material 172 extendsabove a surface of the semiconductor substrate 160. A strap material176A deposited over the first gate material 172 may be masked and/oretched to form the strap 176 over the first gate material 172 asillustrated in FIG. 6E. Conventional masking, etching, doping, anddeposition processes may be used to complete the formation of the RADstructures 170, including the formation of insulator caps 180 andsidewall spacers 178, and the doping of the active areas 162.

Although methods for forming the RAD structures 170 of particularembodiments of the invention are illustrated in FIGS. 6A-6E, it isunderstood that other methods and processes may also be used tofabricate RAD structures 170 according to embodiments of the invention.

When employed with access devices, such as memory devices or othersemiconductor devices, the gate stacks 120 and RAD structures 170 ofembodiments of the invention may reduce GIDL, reduce junction leakage,reduce subthreshold leakage, and increase the drive of the accessdevice. The combination of multiple work functions in the gateelectrodes of the gate stack 120 and RAD structures 170 allowssub-threshold leakage to be controlled or reduced using a high workfunction material while also employing a low work function material toreduce GIDL. The increased margin to GIDL provided by the dual workfunction gate electrode allows the negative access device bias to bepushed more negative, which in turn may reduce the subthreshold leakage.The decreased subthreshold leakage may allow a less negative substratebias to be used with embodiments of the invention to decrease junctionleakage and increase the drive of the access device.

According to other embodiments of the invention, an access device 150′.having one or more RAD structures 170′ with two or more materials havingdifferent work functions may include a RAD structure 170′ having a firstgate material 172′ positioned along at least a portion of the sidewallsof the RAD structure 170′ and a second gate material 174′ at leastpartially surrounded by the first gate material 172′ as illustrated inFIG. 7A. As with other embodiments of the invention, trenches in thesemiconductor substrate 160′ may include a gate-oxide 171′ layer on thesidewalls of the trenches. The first gate material 172′ may bepositioned along at least a portion of the gate-oxide 171′ layer and thesecond gate material 174′ may be positioned with respect to the firstgate material 172′ as illustrated. A barrier layer (not shown) may beformed between the first gate material 172′ and the second gate material174′. The RAD structures 170′ may also include a strap 176′ overlyingthe first gate material 172′ and second gate material 174′ and aninsulator cap 180′ overlying the strap 176′. Gate electrode sidewallspacers 178′ may also be formed with the RAD structures 170′ to completethe trenched gate stack 170′.

According to embodiments of the invention, the second gate material 174′of the RAD structures 170′ may be formed of a material having a higherwork function than the first gate material 172′. For example, the secondgate material 174′ used to form the RAD structures 170′ illustrated inFIG. 7A may include a p-doped polysilicon material and the first gatematerial 172′ may include an n-doped polysilicon material. Othermaterials having differing work functions may also be used to form RADstructures 170′ according to embodiments of the invention.

The RAD structures 170′ of embodiments of the invention may be producedusing fabrication processes used to form conventional semiconductordevices and particularly memory devices. For example, the RAD structures170′ illustrated in FIG. 7A may be formed using conventional CMOS ormemory device fabrication processes similar to the steps illustrated inFIGS. 7B-7D. As illustrated in FIG. 7B, a semiconductor substrate 160′having trenches formed therein may be provided. Oxide 171′ may be grownin the trenches as used with conventional RAD structures. A polysiliconlayer 172A′ may be deposited over the semiconductor substrate 160′ andin the trenches. The polysilicon layer 172A′ may be doped n-typeaccording to conventional doping techniques. An isotropic spacer etchselective to the oxide 171′ may be performed to remove the polysiliconlayer 172A′ in the bottom of a trench, leaving the n-doped polysiliconlayer 172′ on the sidewalls of the trench as illustrated in FIG. 7C. Asecond gate material layer 174A′ formed of a material having a higherwork function than the first gate material 172′ may be deposited overthe substrate 160′ and in the trenches as illustrated in FIG. 7C.Masking and/or etching of the second gate material layer 174A′ may beused to form the second gate material 174′ as illustrated in FIG. 7D.Conventional masking, etching, doping, and deposition processes may beused to complete the formation of a RAD structure 170′, including theformation of a strap 176′, formation of insulator caps 180′, andformation of sidewall spacers 178′ as illustrated in FIG. 7A.

Although methods for forming the RAD structures 170′ of particularembodiments of the invention are illustrated in FIGS. 7B-7D, it isunderstood that other methods and processes may also be used tofabricate RAD structures 170′ according to embodiments of the invention.

When employed with access devices, such as memory devices or othersemiconductor devices, the RAD structures 170′ of embodiments of theinvention may reduce GIDL, reduce junction leakage, reduce subthresholdleakage, and increase the drive of the access device. The combination ofmultiple work functions in the gate electrodes allows sub-thresholdleakage to be controlled or reduced using a high work function materialwhile also employing a low work function material to reduce GIDL. Theincreased margin to GIDL provided by the dual work function gateelectrode allows the negative access device bias to be pushed morenegative, which in turn may reduce the subthreshold leakage. Thedecreased subthreshold leakage may allow a less negative substrate biasto be used with embodiments of the invention to decrease junctionleakage and increase the drive of the access device.

Although the multi-workfunction RAD structures according to embodimentsof the invention have been described with respect to conventional RADstructure configurations, it is also understood that embodiments of theinvention may be incorporated with spherical recessed access devices(SRAD) as well. For example, an SRAD structure according to embodimentsof the invention is illustrated in FIG. 7E. The SRAD structure 170′illustrated in FIG. 7E may include the same characteristics as a RADstructure and may be formed using similar processes.

According to other embodiments of the invention, a gate electrode in anaccess device may be separated into two or more electrically isolatedregions. The two or more electrically isolated regions may be connectedto an access device driver capable of supplying the same or differentvoltages to each of the two or more electrically isolated regions.

An example of an access device 200 incorporating a gate electrode havingtwo or more electrically isolated regions according to embodiments ofthe invention is illustrated in FIG. 8. The access device 200 mayinclude one or more gate stacks 220 formed over a semiconductorsubstrate 210. The gate stacks 220 may be positioned next to or overactive areas 212 in the semiconductor substrate 210 just as conventionalgate stacks are positioned with conventional planar access devices. Thegate stacks 220 may include a gate electrode overlying an oxide layer241. The gate electrode may include a first gate material 242 and asecond gate material 244 separated by an insulator layer 243. Aninsulator cap 246 may overlie the first gate material 242, the secondgate material 244, and the insulator layer 243. The gate stack 220 mayalso include sidewall spacers 248 as known and used with conventionalplanar access device structures.

Gate stacks 220 according to embodiments of the present invention may beincorporated with access devices 200 such as memory devices, CMOSstructures, or other devices and structures where conventional gatestacks may be used.

The semiconductor substrate 210 may include semiconductor substratesconventionally used with or for the fabrication of memory devices,access devices, and other semiconductor devices. In many embodiments,the semiconductor substrate 210 may include one or moresilicon-containing structures such as silicon wafers,silicon-on-insulator structures, or silicon-on-sapphire structures. Theactive areas 212 of the semiconductor substrate 210 may be doped with ann-type, p-type, or other type dopant similar to active areas associatedwith conventional gate stack formations.

The first gate material 242 and the second gate material 244 of a gatestack 220 may be formed of the same material, such as polysilicon. Inother embodiments, the first gate material 242 and the second gatematerial 244 may be formed of different materials or they may be formedof the same material but doped with different dopants to alter thecharacteristics of the gate materials. Although the gate stack 220illustrated in FIG. 8 illustrate gate stacks 220 having two gateelectrode regions—the first gate material 242 defining a first regionand the second gate material 244 defining a second region—it isunderstood that two or more regions may be defined and incorporated withembodiments of the present invention. In such instances, two or moregate material regions may be separated by two or more insulator layers243 positioned in the gate material regions.

The insulator layer 243 positioned between the first gate material 242and the second gate material 244 may include any dielectric layer orsuitable material capable of acting as an insulator between the two gatematerials. For example, the insulator layer 243 may include a layer ofsilicon nitride (SiN), silicon dioxide (SiO₂), or other similarinsulating material.

Insulator caps 246 and sidewall spacers 248 are used with conventionalplanar access devices and the insulator caps 246 and sidewall spacers248 incorporated with the gate stacks 220 of various embodiments of theinvention may include conventional insulator caps and sidewall spacersformed according to conventional fabrication processes.

The gate stacks 220 according to embodiments of the invention may beformed using conventional gate stack fabrication processes, with theformation of the second gate material 244 and the insulator layer 243being added to such processes. For example, processes that may be usedfor the fabrication of the gate stack 220 illustrated in FIG. 8 areillustrated in FIGS. 9A-9D. As illustrated in FIG. 9A, a polysiliconlayer 242A may be deposited over a gate-oxide layer 241 overlying asemiconductor substrate 210. The polysilicon layer 242A may be maskedand etched such that one or more first gate material 242 formationsremain positioned over the oxide layer 241 as illustrated in FIG. 9B. Aninsulator layer 243A may be deposited over the first gate material 242formations. The insulator layer 243A may be etched to remove all but theinsulator layer 243 portions next to the first gate material 242formations as illustrated in FIG. 9C. For example, a vertical isotropicetch may be used to etch the insulator layer 243A such that onlyinsulator layer 243 remains on the sides of the first gate material 242.A second polysilicon layer 244A may be formed over the structure asillustrated in FIG. 9C. The second polysilicon layer 244A may be maskedand etched to form the second gate material 244 formations asillustrated in FIG. 9D. Conventional masking, etching, doping, anddeposition processes may be used to complete the formation of the gatestack 220 including the formation of the insulator caps 246 and sidewallspacers 248, and the doping of the active areas 212.

Although the fabrication processes illustrated in FIGS. 9A-9D show anoxide layer formed over the semiconductor substrate 210 it is understoodthat the oxide layer 241 may include a continuous oxide layer (notshown) across the expanse of the semiconductor substrate 210 that may beetched to the desired form during the processing steps. For example, acontinuous oxide layer (not shown) may be deposited across the entireportion of a semiconductor substrate 210 where a gate stack 220 is to beformed. The components of the gate stack such as the first gate material242, insulator layer 243, second gate material 244, and insulator cap246 may be formed over the continuous oxide layer. The gate stack 220and the continuous oxide layer may then be etched to form the structuresillustrated in FIG. 9D.

Although methods for forming the gate stack 220 of the invention aredescribed with respect to FIGS. 9A-9D, it is understood that othermethods and processes may also be used to fabricate the gate stack 220of the invention and that embodiments of the invention are not limitedby the fabrication processes described.

The gate stacks 220 according to embodiments of the invention may bedriven by an access device driver capable of providing two or morevoltages to the different electrically isolated regions of the gatestacks 220 simultaneously. For instance, the gate stacks 220 illustratedin FIG. 8 may be driven by a access device driver capable of supplying afirst voltage to the first gate material 242 and a second voltage to thesecond gate material 244. The voltages supplied by the access devicedriver may be selected such that the voltages applied to the first gatematerial 242 and the second gate material 244 are the same or different,depending on the desired “on” or “off” state of the gate stack 220.

In some embodiments, a gate stack 220 may include two or more gatematerials. In such instances, an access device driver may be adapted todeliver voltages to each of the gate materials to control the operationsof the gate stack 220.

According to other embodiments of the invention, a RAD structure 270 maybe incorporated into an access device 250. A RAD structure 270 accordingto embodiments of the invention may be similar to a conventional RADstructure having a single gate material. The RAD structures 270 ofparticular embodiments of the invention, however, may include a firstgate material 272 and a second gate material 274 separated by aninsulator layer 273. For example, a RAD structure 270 according toparticular embodiments of the invention is illustrated in FIG. 10.

The RAD structure 270 illustrated in FIG. 10 includes two gatematerials, a first gate material 272 and a second gate material 274,positioned in a trench in a semiconductor substrate 210. A gate oxidelayer 271 may coat or overlie the sides of the trench in thesemiconductor substrate 210. The first gate material 272 and the secondgate material 274 may be separated by an insulator layer 273. The RADstructures 270 may be positioned next to or over active areas 262 in thesemiconductor substrate 210 just as RAD structures are positioned withconventional access devices. An insulator cap 276 may overlie the gatematerials of a RAD structure 270 and sidewall spacers 278 may border thesides of the RAD structure 270 as illustrated in FIG. 10. The insulatorcap 276 and sidewall spacers 278 may be similar to insulator caps andsidewall spacers employed with conventional RAD devices.

Although the RAD structure 270 illustrated in FIG. 10 shows a first gatematerial 272 and a second gate material 274 separated by an insulatorlayer 273, embodiments of the invention may include two or more gatematerials separated by two or more insulator layers.

RAD structures 270 according to embodiments of the invention may beincorporated with access devices 250 such as memory devices, CMOSstructures, or other devices and structures where RAD structures 270 maybe used.

Semiconductor substrates 210 may include semiconductor substratesconventionally used with or for the fabrication of memory devices,access devices, and other semiconductor devices. In many embodiments,the semiconductor substrate 210 may include one or moresilicon-containing structures such as silicon wafers,silicon-on-insulator structures, or silicon-on-sapphire structures. Theactive areas 262 of the semiconductor substrate 210 may be doped with ann-type, p-type, or other type dopant similar to active areas associatedwith conventional RAD structure formations.

The gate materials forming the first gate material 272 and the secondgate material 274 may include materials used to form conventional gateelectrodes. For example, the gate materials used with the RAD structures270 according to embodiments of the invention may include materials suchas polysilicon materials. The same gate material may be used to form thefirst gate material 272 and the second gate material 274 or the two gatematerials may be formed from different gate materials. In otherembodiments, the first gate material 272 and the second gate material274 may be doped with different dopants to alter the characteristics ofthe gate materials.

The insulator layer 273 positioned between the first gate material 272and the second gate material 274 may include any dielectric layer orsuitable material capable of acting as an insulator between the two gatematerials. For example, the insulator layer 273 may include a layer ofsilicon nitride (Si₃N₄), silicon dioxide (SiO₂), or other similarinsulating material.

The RAD structures 270 according to embodiments of the invention may beformed using conventional RAD structure fabrication processes. Forexample, a process that may be used to fabricate a RAD structureaccording to embodiments of the invention is illustrated in FIGS.11A-11D.

RAD structures 270 according to embodiments of the invention may beformed in a trench in a semiconductor device wherein the trench includesa gate-oxide layer as may be fabricated for conventional RAD structures.As illustrated in FIG. 11A, a polysilicon layer 272A may be depositedover a semiconductor substrate 210 having trenches lined with a gateoxide 271 material. The polysilicon layer 272A may be etched, leaving afirst gate material 272 deposited over the gate oxide layer 271 in thebottom of a trench as illustrated in FIG. 11B. An insulator materiallayer 273A deposited over the first gate material 272 and the gate oxidelayer 271 may be etched to form the insulator layer 273 over the firstgate material 272. The etching of the insulator material layer 273A maybe performed so that the gate oxide layer 271 remains on the surface ofthe trenches in the semiconductor substrate 210. A second polysiliconlayer 274A may be deposited over the semiconductor substrate 210 and inthe trenches, covering the insulator layer 273 and filling the trenchesas illustrated in FIG. 11C. Selective masking and etching of the secondpolysilicon layer 274A forms the second gate material 274 formations asillustrated in FIG. 11D.

Conventional masking, etching, doping, and deposition processes may beused to complete the formation of the RAD structures 270 including theformation of the insulator caps 276 and sidewall spacers 278, and thedoping of the active areas 262. In addition, masking of the trenches,contacts between RAD structures, and metal layers above the RADstructures may be performed such that contact may be made to the bottomportion of the RAD structure 270, and the first gate material 272, aswell as to the top portion of the RAD structure 270 and the second gatematerial 274. The contact may be connected to an access device drivercapable of supplying desired voltages to the first gate material 272 andsecond gate material 274.

Although methods for fabricating RAD structures 270 of the invention aredescribed with respect to FIGS. 11A-11D, it is understood that othermethods and processes may also be used to fabricate the RAD structures270 of the invention and that embodiments of the invention are notlimited by the fabrication processes described.

The RAD structures 270 according to embodiments of the invention may bedriven by an access device driver capable of providing two or morevoltages to the RAD structure 270 simultaneously. For example, the RADstructure 270 illustrated in FIG. 10 may be driven by an access devicedriver capable of supplying a first voltage to the first gate material272 and a second voltage to the second gate material 274. The voltagessupplied by the access device driver may be selected such that thevoltages applied to the first gate material 272 and the second gatematerial 274 are the same or different, depending on the desired “on” or“off” state of the RAD structure 270.

In some embodiments, the RAD structures 270 may include two or more gatematerials. In such instances, an access device driver may be adapted todeliver voltages to each of the gate materials to control the operationsof the RAD structures 270.

The gate stacks 220 and RAD structures 270 having multiple electricallyisolated regions according to embodiments of the invention may reducethe amount of gate induced drain leakage (GIDL), junction leakage, andsubthreshold leakage while increasing the drive of the access device.The gate stacks 220 and RAD structures 270 reduce the amount of GIDLwhile preserving a negative gate electrode bias. This may beaccomplished by applying different voltages to the first and second gateelectrodes of the gate stacks 220 and RAD structures 270. Therefore, inthe “off” state, one of the negative gate electrode bias may be mademore negative while the other remains “off,” but at a less negativebias—thereby decreasing GIDL current. The more negative word line biason one portion of the gate results in decreased subthreshold leakage.Further, a less negative substrate bias may be used, which woulddecrease junction leakage and increase the drive of the access device.

According to still other embodiments of the invention, planar orrecessed access devices may also include gate electrodes comprised ofdiodes. The incorporation of a diode structure with the gate electrodewould allow two voltages to be applied to the electrode structure: afirst voltage across the anode of the diode and a second voltage acrossthe cathode of the diode.

An access device 300 utilizing a gate stack 320 constructed of a diodeaccording to embodiments of the invention is illustrated in FIG. 14. Theaccess device 300 may include one or more gate stacks 320 formed over asemiconductor substrate 310. The gate stacks 320 maybe positioned nextto or over active areas such as storage capacitors 312 and bitlinecontacts 313 in the semiconductor substrate 310 just as conventionalgate stacks are positioned with conventional access devices. The gatestacks 320 may include a gate electrode overlying an oxide layer 321,wherein the gate electrode comprises an anode 324 and a cathode 322. Theanode 324 may be positioned closest to a bitline contact 313 active areawhile the cathode 322 may be positioned closest to the storage capacitor312 active areas. An insulator cap 330 may overlie the gate electrodeand sidewall spacers 328 may be positioned on the sides of the gatestack 320 in a manner similar to conventional gate stacks.

The gate stacks 320 may be incorporated with access devices 300 such asmemory devices, CMOS structures, or other devices and structures wheregate stacks 320 may be used.

The semiconductor substrate 310 may include semiconductor substratesconventionally used with or for the fabrication of memory devices,access devices, and other semiconductor devices. In many embodiments,the semiconductor substrate 310 may include, but is not limited to, oneor more silicon containing materials such as silicon,silicon-on-insulator structures, or silicon-on-sapphire structures. Thebitline contacts 313 and storage capacitor 312 of the semiconductorsubstrate 310 may be doped with an n-type, p-type, or other type dopantto form the desired active areas, which are similar to those formed inconventional gate stack formations.

The insulator caps 330 and sidewall spacers 328 may include materialsused to form the insulator caps and sidewall spacers of conventionalgate stack devices.

The anode 324 of the gate stack 320 may be formed of materialsconventionally used to form anodes in semiconductor devices. The anode324 may also be formed of a doped material such as a p-type dopedmaterial. In some embodiments, the anode 324 may be formed of aRuthenium-Tantalum (Ru_(x)Ta_(y)) metal alloy or a tantalum nitride(TaN) metal alloy.

The cathode 322 of the gate stack 320 may be formed of materialsconventionally used to form cathodes in semiconductor devices. Thecathode 322 may also be formed of a doped material such as an n-typedoped material. In some embodiments, the cathode 322 may be formed of aRuthenium-Tantalum (Ru_(x)Ta_(y)) metal alloy or a tantalum nitride(TaN) metal alloy.

According to some embodiments of the invention, a gate stack 320 of anaccess device 300, such as the gate stack 320 illustrated in FIG. 14,may be fabricated according to the steps illustrated in FIGS. 15A- 15D.The gate stacks 320 of embodiments of the present invention may beformed over semiconductor substrates 310 having oxide layers 321 formedthereon as with a conventional gate stack fabrication method. The oxidelayer 321 may be a discontinuous oxide layer 321 as illustrated in FIG.15A or a continuous oxide layer which is etched or otherwise partiallyremoved to form the oxide layer 321 illustrated in FIG. 15A. Asillustrated in FIG. 15A, an anode material 324A may be deposited over asemiconductor substrate 310 having oxide layers 321. The anode material324A may be masked and etched according to conventional techniques toform anode 324 portions of the gate stack 320 as illustrated in FIG.15B. A cathode material 322A may be deposited over the anode 324portions of the gate stack 320 as well as the semiconductor substrate310 having oxide layers 321 as illustrated in FIG. 15C. The cathodematerial 322A and anode portions may be masked and etched to form theanode 324 and cathode 322 diode structures of the gate stacks 320 asillustrated in FIG. 15D. Conventional gate stack fabrication techniquesmay then be used to form the insulator cap 330 and sidewall spacers 328,completing the formation of the gate stacks 320. The active areas in thesemiconductor substrate 310, such as the bitline contacts 313 andstorage capacitors 312, may also be formed using conventional methods offabrication. For example, the bitline contacts 313 and the storagecapacitors 312 may be doped with an n-type dopant to form N+ dopedactive areas.

Although the anode 324 portions of the gate stacks 320 illustrated inFIGS. 15A-15D are shown as being fabricated before the cathode 322portions of the gate stacks 320, it is understood that the order offormation of the cathode 322 portions and anode 324 portions is notcritical. Therefore, the cathode 322 portions may be formed before theanode 324 portions according to embodiments of the invention.

In addition, after the initial formation of the anode 324 portions andcathode 322 portions of the gate electrode, the structures may bemasked, etched, polished, or otherwise formed such that the center ofthe gate stack 320 is positioned at the interface of the anode 324portions and the cathode portions 322 of the gate stack. For instance,chemical mechanical planarization (CMP) processes may be used to formthe gate stack 320 to the desired height and masking and etchingprocesses may be used to ensure that the center of the gate stack 320structure is located at the boundary of the anode 324 and the cathode322.

According to embodiments of the invention, the anode material 324A andcathode material 322A may be selected such that the work function of thetwo materials is different. For example, in some embodiments the cathodematerial 322A and anode material 324A may each compriseRuthenium-Tantalum which may be represented by the chemical formulaRu_(x)Ta_(y) wherein x and y may be selected according to the desiredwork functions for the diode. For example, the anode 324 may be formedof an Ru_(x)Ta_(y) material wherein x and y are selected such that theanode 324 exhibits a work function of about 5.0 eV. The cathode 322 maybe formed of an Ru_(x)Ta_(y) material wherein x and y are selected suchthat the cathode 322 exhibits a work function of about 4.2 eV. Othervalues of x and y may be selected such that the work functions of thetwo materials is different.

The gate stacks 320 according to embodiments of the invention may beformed as one long diode having approximately equal cathode 322 andanode 324 regions within the gate stack 320. The anode 324 regions maybe positioned closest to the bitline contacts 313 while the cathode 322regions may be positioned closest to the storage capacitors 312. In an“off” state, the anode 324 of a gate stack 320 is held at a negativeword line voltage while the cathode 322 is held at a higher voltage thanthe anode 324. The difference in voltages between the cathode 322 andanode 324 creates a reverse bias across the diode. The bias level of thecathode 322 may be determined by the breakdown voltage of the reversedbiased diode gate. The cathode 322 region bias level may decrease thevoltage difference between the storage capacitors 312 and the gate stack320, which in turn may decrease the electric field in the gate stack 320area. The decreased electric field in the gate stack 320 area may helpto reduce the gate-induced drain leakage in a gate stack 320 formedaccording to embodiments of the invention. In an “on” state, the anode324 and the cathode 322 of the gate electrode or gate stack 320 are bothdriven to the same positive level as with conventional gate stackdevices.

In still other embodiments of the invention, the diode of the gatestacks 320 may include a Schottky-Barrier type diode. In such instances,the anode 324 may be a metal layer and the cathode 322 may be apolysilicon material that is doped, for example a polysilicon materialthat is slightly doped N+. Embodiments of the invention may also includegate stacks 320 formed of Schottky-Barrier type diodes.

In other embodiments of the invention, an access device 350 may includeone or more recessed access device (RAD) structures 370 comprisingdiodes as illustrated in FIG. 16. The RAD structures 370 may include adiode comprised of an anode 374 and a cathode 372 formed in a trench ina semiconductor substrate 360. The anode 374 may be formed in the bottomof a trench and the cathode 372 may lie on top of the anode 374 and mayextend beyond the surface of the semiconductor substrate 360. The RADstructures 370 may be positioned in trenches in a semiconductorsubstrate 360 just as conventional RAD structures are positioned. Thetrenches in the semiconductor substrate 360 may be lined with oxide 371layers such that the cathode 372 and anode 374 may be in contact withthe oxide 371 layer rather than a wall of a trench. The RAD structures370 may also include an insulator cap 376 and sidewall spacers 378similar to those used with conventional RAD structures.

The RAD structures 370 may be incorporated with access devices 350 suchas memory devices, CMOS structures, or other conventional devices andstructures employing the use of RAD structures 370.

The semiconductor substrate 360 may include semiconductor substratesconventionally used with or for the fabrication of memory devices,access devices, and other semiconductor devices. In many embodiments,the semiconductor substrate 360 may include one or moresilicon-containing structures such as silicon wafers,silicon-on-insulator structures, or silicon-on-sapphire structures. Thebitline contacts 363 and storage capacitors 362 of the semiconductorsubstrate 360 may be doped with an n-type, p-type, or other type dopantto form the desired active areas, which are similar to those formed withconventional RAD structure formations.

The insulator caps 376 and sidewall spacers 378 may include materialsused to form the insulator caps and sidewall spacers of conventionalgate stack devices.

The anode 374 of the RAD structure 370 may be formed of materialsconventionally used to form anodes in semiconductor devices. The anode374 may also be formed of a doped material such as a p-type dopedmaterial. In some embodiments, the anode 374 may be formed of aRuthenium-Tantalum (Ru_(x)Ta_(y)) metal alloy or a tantalum nitride(TaN) metal alloy.

The cathode 372 of the RAD structure 370 may be formed of materialsconventionally used to form cathodes in semiconductor devices. Thecathode 372 may also be formed of a doped material such as an n-typedoped material. In some embodiments, the cathode 372 may be formed of aRuthenium-Tantalum (Ru_(x)Ta_(y)) metal alloy or a tantalum nitride(TaN) metal alloy.

According to some embodiments of the invention, a RAD structure 370,such as that illustrated in FIG. 16, may be fabricated according to theprocesses illustrated in FIGS. 17A-17D. A RAD structure 370 may befabricated in the trenches of a simiconductor substrate 360 as withconventional RAD structures. The trenches may include an oxide 371layer, such as a gate oxide layer, covering the surfaces of thetrenches. As illustrated in FIG. 17A, an anode material 374A may bedeposited over and in an oxide 371 layered trench in a semiconductorsubstrate 360. The anode material 374A may then be masked and etchedaccording to conventional processes to leave a portion of the anodematerial 374A in the trenches which forms the anode 374 of the RADstructure 370 as illustrated in FIG. 17B. The etching of the anodematerial 374A to form the anode 374 may be selective to the oxide 371layer such that the oxide 371 layer remains on the walls of thetrenches. As illustrated in FIG. 17C, a cathode material 372A may thenbe deposited over the semiconductor substrate 360 and in the trenchesover the anode 374. Deposition of the cathode material 372A may beaccomplished using conventional deposition processes. The cathodematerial 372A may be masked and etched according to conventionalprocesses to form the cathode 372 structure illustrated in FIG. 17D.Conventional RAD structure fabrication processes may be employed to forman insulator cap 376 and sidewall spacers 378 of the RAD structure 370according to embodiments of the invention. The active areas in thesemiconductor substrate 360, such as the bitline contacts 363 andstorage capacitors 362, may also be formed using conventional processesfor forming active areas. For example, the bitline contacts 363 and thestorage capacitors 362 may be doped with an n-type dopant to form N+doped active areas.

According to embodiments of the invention, the anode material 374A andcathode material 372A may be selected such that the work function of thetwo materials is different. For example, in some embodiments the cathodematerial 372A and anode material 374A may each compriseRuthenium-Tantalum which may be represented by the chemical formulaRu_(x)Ta_(y) wherein x and y may be selected according to the desiredwork functions for the diode. The anode 374 may be formed of anRu_(x)Ta_(y) material wherein x and y are selected such that the anode374 exhibits a work function of about 5.0 eV. The cathode 372 may beformed of an Ru_(x)Ta_(y) material wherein x and y are selected suchthat the cathode 372 exhibits a work finction of about 4.2 eV. Othervalues of x and y may be selected such that the work functions of theformed materials are different.

The gate electrodes formed by the RAD structures 370 of particularembodiments of the invention may be formed as long diodes in thetrenches of the semiconductor substrate 360. The bottom portion of theRAD structure 370 in the trenches of the semiconductor substrate 360 isthe anode 374 and the top portion is the cathode 372 of the diode. Whenthe recessed access device 350 is in an “off” state, the anode 374 maybe held at a negative word line voltage while the cathode 372 may beheld at a higher voltage to create a reverse biased diode. Thedifference in voltages between the cathode 372 and the anode 374 maycreate a reverse bias across the diode. The bias level of the cathode372 may be determined by the breakdown voltage of the reversed biaseddiode gate. The cathode 372 region bias level may decrease the voltagedifference between storage capacitors 362 and the RAD structure 370,which in turn may decrease the electric field in the gate electrodearea. The decreased electric field in the RAD structure 370 area mayhelp to reduce the gate-induced drain leakage in a RAD structure 370formed according to embodiments of the invention. In an “on” state, boththe anode 374 and the cathode 372 may be driven to the same positivelevel as with conventional recessed access devices.

In still other embodiments of the invention, the diode of the RADstructure 370 may be formed such that a Schottky-Barrier diode is formedin the RAD structure 370. In such instances, the anode 374 may be ametal layer deposited in the trenches of the semiconductor substrate 360and recessed so that it only remains in the bottom of the trenches. Thecathode 372 may be a polysilicon material deposited over the metal anode374 that is doped, for example a polysilicon material that is slightlydoped N+ Embodiments of the invention may also include RAD structures370 formed of other Schottky-Barrier type diodes.

The gate stacks 320 and RAD structures 370 according to embodiments ofthe invention may use two separate access device voltages to bias thediode formed by the anodes 374 and cathodes 372 of the gate electrodes.An access device driver, such as those described herein, capable ofproviding multiple voltage levels may be combined with the gate stacks320 and RAD structures 370 to carry out particular embodiments of theinvention.

According to other embodiments of the invention, an access device drivermay be capable of driving the devices and structures of embodiments ofthe invention. Access device drivers and driver circuits used withembodiments of the invention may be able to turn two or more portions ofthe gate electrodes of a gate stack or recessed access device “on” and“off.” The access device drivers of embodiments of the invention aremodified to provide separate bias levels onto the anode and cathoderegions of a diode in a gate electrode or onto the electrically isolatedregions of a gate electrode for a planar or recessed access device.

For example, access device drivers according to embodiments of theinvention may be capable of applying a negative gate electrode voltageto one portion of a gate electrode and a ground voltage to anotherportion of the gate electrode. Thus, the driver would be able to supplytwo or more voltages to the gate electrode of a planar or recessedaccess device.

An example of an access device driver that may be used according toembodiments of the invention is illustrated in FIG. 13. The accessdevice driver may include two outputs which may accommodate one or morediodes connected between the outputs as illustrated in FIG. 13.

For example, the access device driver illustrated in FIG. 13 may beincorporated with an access device to operate the gate stacks 220 or RADstructures 270 having two or more electrically isolated regions such asthose illustrated in FIGS. 7 and 9. The contact of the access devicedriver labeled 1 may be connected to the second gate materials of a gatestack 220 or a RAD structure 270, while the contact of the access devicedriver labeled 2 may be connected to the first gate material of the samegate stack 220 or RAD structure 270. In this manner, differing biaslevels may be applied by the access device driver to the first gatematerial and second gate material of a gate stack 220 or RAD structure270.

In another embodiment, an access device driver such as that illustratedin FIG. 12 may be used to supply separate bias levels to a gate stack orgate electrode of a planar or recessed access device, having a diode inthe gate electrode. For example, the access device driver illustrated inFIG. 12 may be used to supply voltages to the anodes and cathodes of theplanar and recessed gates electrodes illustrated in FIGS. 13 and 16,respectively.

The access device drivers according to embodiments of the invention mayalso include resistive devices (not shown) positioned between one of theoutputs of the access device driver and the access device, such as arecessed or planar access device. In case of a defect or short betweentwo, or more, electrically isolated regions of an access device, thepresence of a resistive device between one of the outputs of the accessdevice driver and one of the electrically isolated regions in the accessdevice may limit the current path between the two, or more, separatepower supplies utilized by the driver.

The ability to apply different bias levels to the different portions ofthe planar or recessed access device gate electrodes allows the amountof gate induced drain leakage (GIDL) to be controlled. Furthermore, theability to turn one portion of the gate electrode “off” at a lowervoltage than the other ensures that subthreshold leakage may beminimized. Furthermore, if subthreshold leakage is minimized, thesubstrate bias may be reduced to decrease junction leakage.

The access device drivers according to embodiments of the invention maybe used with CMOS applications, memory devices such as DRAM, and withany other semiconductor devices where it may be desirable to turndifferent portions of a gate electrode to different “off” or “on” statesto control or reduce GIDL, subthreshold leakage, or junction leakage.

Having thus described certain currently preferred embodiments of thepresent invention, it is understood that the invention defined by theappended claims is not to be limited by particular details set forth inthe above description, as many apparent variations thereof arecontemplated without departing from the spirit or scope thereof ashereinafter claimed.

1. A gate electrode, comprising: a first gate material having a firstwork function associated therewith; and a second gate material having asecond work function associated therewith.
 2. The gate electrode ofclaim 1, wherein the first work function associated with the first gatematerial is different than the second work function associated with thesecond gate material.
 3. The gate electrode of claim 1, furthercomprising a separator between the first gate material and the secondgate material.
 4. The gate electrode of claim 3, wherein the separatorcomprises a material selected from the group consisting of a nitride, anoxide, a silicide, a conductive metal, and a metallic alloy.
 5. The gateelectrode of claim 3, further comprising a conductive strap in contactwith the first gate material and the second gate material.
 6. The gateelectrode of claim 2, further comprising a trench in a semiconductorsubstrate, wherein the first gate material and at least a portion of thesecond gate material are deposited in the trench of the semiconductorsubstrate.
 7. The gate electrode of claim 1, further comprising aconductive material separating the first gate material and the secondgate material.
 8. The gate electrode of claim 7, wherein the conductivematerial comprises a material selected from the group consisting ofmetals, doped silicon, doped polysilicon, and conductive siliconmaterials.
 9. The gate electrode of claim 1, wherein the first gatematerial is electrically isolated from the second gate material.
 10. Thegate electrode of claim 9, wherein the first work function is differentthan the second work function.
 11. The gate electrode of claim 9,further comprising at least one additional gate material, wherein the atleast one additional gate material is electrically isolated from thefirst gate material and the second gate material.
 12. The gate electrodeof claim 9, wherein the first gate material and the second gate materialeach comprise a material selected from the group consisting ofpolysilicon, doped polysilicon, silicon, and doped silicon.
 13. The gateelectrode of claim 9, wherein the first gate material is electricallyisolated from the second gate material in a trench of a recessed accessdevice.
 14. The gate electrode of claim 9, further comprising aninsulator positioned between the first gate material and the second gatematerial, wherein the insulator provides electrical isolation betweenthe first gate material and the second gate material.
 15. The gateelectrode of claim 14, wherein the insulator comprises a materialselected from the group consisting of silicon nitride, and silicondioxide.
 16. The gate electrode of claim 1, wherein the first gatematerial comprises an anode and the second gate electrode comprises acathode.
 17. The gate electrode of claim 16, wherein the first gatematerial is a p-type material.
 18. The gate electrode of claim 16,wherein the second gate material is an n-type material.
 19. A planaraccess device, comprising: a semiconductor substrate; an oxide layerpositioned over the semiconductor substrate; a first gate materialoverlying the oxide layer; a second gate material overlying the oxidelayer; an electrical connection between the first gate material and thesecond gate material; and an insulator cap overlying the first gatematerial and the second gate material.
 20. The planar access device ofclaim 19, further comprising at least two sidewall spacers positioned onthe sides of the gate stack and isolating the first gate material andthe second gate material between the at least two sidewall spacers andunder the insulator cap.
 21. The planar access device of claim 19,further comprising a separator positioned between the first gatematerial and the second gate material.
 22. The planar access device ofclaim 19, wherein the first gate material and the second gate materialeach contact the oxide layer.
 23. The planar access device of claim 19,wherein the first gate material comprises a material selected from thegroup consisting of polysilicon, doped polysilicon, and metal.
 24. Theplanar access device of claim 19, wherein the second gate materialcomprises a material selected from the group consisting of polysilicon,doped polysilicon, and metal.
 25. The planar access device of claim 19,wherein the first gate material comprises a doped polysilicon materialand the second gate material comprises a doped polysilicon material,wherein the first gate material and the second gate material are dopedwith different dopants.
 26. The planar access device of claim 19,wherein the electrical connection comprises a conductive strap incontact with the first gate material and the second gate material. 27.The planar access device of claim 26, wherein the conductive strapcomprises a conductive material selected from the group consisting ofmetal, doped polysilicon, doped silicon, and a metal alloy.
 28. Theplanar access device of claim 26, wherein the conductive strap comprisesa conductive strap positioned between the first gate material and thesecond gate material.
 29. The planar access device of claim 26, whereinthe conductive strap comprises a conductive strap positioned over thefirst gate material and the second gate material.
 30. A recessed accessdevice, comprising: a semiconductor substrate; at least one trench inthe semiconductor substrate; an oxide layer positioned over sidewalls ofthe at least one trench; a first gate material in a bottom portion ofthe at least one trench and overlying at least a portion of the oxidelayer; a second gate material in the at least one trench and overlyingthe first gate material; an electrical connection between the first gatematerial and the second gate material; and an insulator cap overlyingthe second gate material.
 31. The recessed access device of claim 30,further comprising a metal barrier positioned between the first gatematerial and the second gate material.
 32. The recessed access device ofclaim 30, wherein the first gate material and the second gate materialeach contact the oxide layer.
 33. The recessed access device of claim30, wherein the first gate material comprises a material selected fromthe group consisting of polysilicon, doped polysilicon, and metal. 34.The recessed access device of claim 30, wherein the second gate materialcomprises a material selected from the group consisting of polysilicon,doped polysilicon, and metal.
 35. The recessed access device of claim30, wherein the first gate material comprises a doped polysiliconmaterial and the second gate material comprises a doped polysiliconmaterial, wherein the first gate material and the second gate materialare doped with different dopants.
 36. The recessed access device ofclaim 30, wherein the electrical connection comprises a barrier layer incontact with the first gate material and the second gate material. 37.The recessed access device of claim 36, wherein the barrier layercomprises a material selected from the group consisting of metal, dopedpolysilicon, doped silicon, and an insulator material.
 38. The recessedaccess device of claim 36, wherein the barrier layer comprises a barrierlayer positioned between the first gate material and the second gatematerial.
 39. A recessed access device, comprising: a semiconductorsubstrate; at least one trench in the semiconductor substrate; an oxidelayer positioned over sidewalls of the at least one trench; a first gatematerial positioned over at least a portion of the sidewalls of the atleast one trench; a second gate material in the at least one trench andat least partially surrounded by the first gate material; and aninsulator cap overlying the first gate material and the second gatematerial.
 40. The recessed access device of claim 39, wherein the firstgate material and the second gate material each contact the oxide layer.41. The recessed access device of claim 39, wherein the first gatematerial comprises a material selected from the group consisting ofpolysilicon, doped polysilicon, and metal.
 42. The recessed accessdevice of claim 39, wherein the second gate material comprises amaterial selected from the group consisting of polysilicon, dopedpolysilicon, and metal.
 43. The recessed access device of claim 39,wherein the first gate material comprises a doped polysilicon materialand the second gate material comprises a doped polysilicon material,wherein the first gate material and the second gate material are dopedwith different dopants.
 44. The recessed access device of claim 39,wherein the second gate material comprises a material having a higherwork function than the first gate material.
 45. A planar access device,comprising: a semiconductor substrate; an oxide layer positioned overthe semiconductor substrate; a first gate material overlying the oxidelayer; a second gate material overlying the oxide layer; an insulatorbetween the first gate material and the second gate material; and aninsulator cap overlying the first gate material and the second gatematerial.
 46. The planar access device of claim 45, further comprisingat least two sidewall spacers positioned on sides of the gate stack andisolating the first gate material and the second gate material betweenthe at least two sidewall spacers and under the insulator cap.
 47. Theplanar access device of claim 45, wherein the insulator comprises amaterial selected from the group consisting of silicon nitride andsilicon dioxide.
 48. The planar access device of claim 45, wherein thefirst gate material and the second gate material each contact the oxidelayer.
 49. The planar access device of claim 45, wherein the first gatematerial comprises a material selected from the group consisting ofpolysilicon, doped polysilicon, and metal.
 50. The planar access deviceof claim 45, wherein the second gate material comprises a materialselected from the group consisting of polysilicon, doped polysilicon,and metal.
 51. The planar access device of claim 45, wherein the firstgate material comprises a doped polysilicon material and the second gatematerial comprises a doped polysilicon material, wherein the first gatematerial and the second gate material are doped with different dopants.52. The planar access device of claim 45, further comprising: a firstcontact between the first gate material and a first voltage supply; anda second contact between the second gate material and a second voltagesupply.
 53. The planar access device of claim 52, wherein the firstvoltage supply and the second voltage supply originate from an accessdevice driver.
 54. The planar access device of claim 52, wherein thefirst voltage supply and the second voltage supply are configured toprovide the same or different voltages to the first contact and thesecond contact.
 55. A recessed access device, comprising: asemiconductor substrate; at least one trench in the semiconductorsubstrate; an oxide layer positioned over sidewalls of the at least onetrench; a first gate material in a bottom portion of the at least onetrench and overlying at least a portion of the oxide layer; an insulatoroverlying the first gate material; a second gate material in the atleast one trench and overlying the insulator; and an insulator capoverlying the second gate material.
 56. The recessed access device ofclaim 55, wherein the first gate material and the second gate materialeach contact the oxide layer.
 57. The recessed access device of claim55, wherein the first gate material comprises a material selected fromthe group consisting of polysilicon, doped polysilicon, and metal. 58.The recessed access device of claim 55, wherein the second gate materialcomprises a material selected from the group consisting of polysilicon,doped polysilicon, and metal.
 59. The recessed access device of claim55, wherein the first gate material comprises a doped polysiliconmaterial and the second gate material comprises a doped polysiliconmaterial, wherein the first gate material and the second gate materialare doped with different dopants.
 60. The recessed access device ofclaim 55, wherein the insulator comprises a material selected from thegroup consisting of silicon nitride and silicon dioxide.
 61. Therecessed access device of claim 55, further comprising: a first contactbetween the first gate material and a first voltage supply; and a secondcontact between the second gate material and a second voltage supply.62. The recessed access device of claim 61, wherein the first voltagesupply and the second voltage supply originate from an access devicedriver.
 63. The recessed access device of claim 61, wherein the firstvoltage supply and the second voltage supply are configured to providethe same or different voltages to the first contact and the secondcontact.
 64. A planar access device, comprising: a semiconductorsubstrate; an oxide layer positioned over the semiconductor substrate; acathode gate material overlying the oxide layer; an anode gate materialoverlying the oxide layer and positioned next to the cathode gatematerial, wherein the anode gate material and the cathode gate materialform a diode; and an insulator cap overlying the cathode gate materialand the anode gate material.
 65. The planar access device of claim 64,further comprising at least two sidewall spacers positioned on sides ofthe gate stack and isolating the cathode gate material and the anodegate material between the at least two sidewall spacers and under theinsulator cap.
 66. The planar access device of claim 64, wherein thecathode gate material and the anode gate material each contact the oxidelayer.
 67. The planar access device of claim 64, wherein the cathodegate material comprises a material selected from the group consisting ofpolysilicon, doped polysilicon, metal, ruthenium-tantalum, and tantalumnitride.
 68. The planar access device of claim 64, wherein the anodegate material comprises a material selected from the group consisting ofpolysilicon, doped polysilicon, metal, ruthenium-tantalum, and tantalumnitride.
 69. The planar access device of claim 64, wherein the cathodegate material comprises an n-type cathode material.
 70. The planaraccess device of claim 64, wherein the anode gate material comprises ap-type anode material.
 71. The planar access device of claim 64, whereinthe cathode gate material comprises a doped polysilicon material and theanode gate material comprises a doped polysilicon material, wherein thecathode gate material and the anode gate material are doped withdifferent dopants.
 72. The planar access device of claim 64, furthercomprising: a first contact between the cathode gate material and afirst voltage supply; and a second contact between the anode gatematerial and a second voltage supply.
 73. The planar access device ofclaim 72, wherein the first voltage supply and the second voltage supplyoriginate from an access device driver.
 74. The planar access device ofclaim 72, wherein the first voltage supply and the second voltage supplyare configured to provide the same or different voltages to the firstcontact and the second contact.
 75. The gate stack of claim 64, whereinthe diode comprises a Schottky-Barrier diode.
 76. A recessed accessdevice, comprising: a semiconductor substrate; at least one trench inthe semiconductor substrate; an oxide layer positioned over sidewalls ofthe at least one trench; an anode gate material in a bottom portion ofthe at least one trench and overlying at least a portion of the oxidelayer; a cathode gate material in the at least one trench and overlyingthe anode gate material, wherein the anode gate material and the cathodegate material form a diode; and an insulator cap overlying the cathodegate material.
 77. The recessed access device of claim 76, wherein theanode gate material and the cathode gate material each contact the oxidelayer.
 78. The recessed access device of claim 76, wherein the anodegate material comprises a material selected from the group consisting ofpolysilicon, doped polysilicon, metal, ruthenium-tantalum, and tantalumnitride.
 79. The recessed access device of claim 76, wherein the cathodegate material comprises a material selected from the group consisting ofpolysilicon, doped polysilicon, metal, ruthenium-tantalum, and tantalumnitride.
 80. The recessed access device of claim 76, wherein the anodegate material comprises a doped polysilicon material and the cathodegate material comprises a doped polysilicon material, wherein the anodegate material and the cathode gate material are doped with differentdopants.
 81. The recessed access device of claim 76, wherein the cathodegate material comprises an n-type cathode material.
 82. The recessedaccess device of claim 76, wherein the anode gate material comprises ap-type anode material.
 83. The recessed access device of claim 76,further comprising: a first contact between the cathode gate materialand a first voltage supply; and a second contact between the anode gatematerial and a second voltage supply.
 84. The recessed access device ofclaim 83, wherein the first voltage supply and the second voltage supplyoriginate from an access device driver.
 85. The recessed access deviceof claim 83, wherein the first voltage supply and the second voltagesupply are configured to provide the same or different voltages to thefirst contact and the second contact.
 86. The recessed access device ofclaim 76, wherein the diode comprises a Schottky-Barrier diode.
 87. Aaccess device driver, comprising an access device driver capable ofsupplying at least two voltages to an access device.
 88. The accessdevice driver of claim 87, wherein the access device driver comprisesthe access device driver illustrated in FIG.
 12. 89. The access devicedriver of claim 87, wherein the access device driver comprises theaccess device driver illustrated in FIG.
 13. 90. The access devicedriver of claim 87, further comprising a resistor, wherein the resistoris in electrical communication with at least one of the at least twovoltages supplied by the access device driver.